Hybrid Processors—Combining FPGAs with Traditional Microprocessors
Intel is working on the Larrabee architecture which is a next generation gpu with 16 cores (or more) that eventually will be merged with standard microprocessors to create a hybrid processor.
AMD’s hybrid processor is called Fusion and has been in the news for so long it now has its own Wikipedia page.
Berkeley researches this area in a program called Chess with applications in systems, control, autonomous systems, modeling and computation.
The key to achieving performance with a hybrid processor is software that maps an application efficiently onto the multiple cores. In this survey the software platform needs to provide performance, advanced debug support, determinism, and thread locking to fully engage the potential of a hybrid. Numerous examples of compilers offer solutions based on C and other languages. FPGAs can process iterative functions such as matrix multiplication more efficiently than traditional processors while file I/O and housekeeping tasks are not as well suited. In this paper the authors argue for a simplistic software mapping of functions into hardware.